`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/12/11 14:20:12
// Design Name:
// Module Name: testComputer
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module testComputer(

  );
  logic clk, rst, uart_rx_pin, uart_tx_pin, over, succ;

  logic [7:0] uart_rx_data;
  logic uart_rx_done;

  uart_rx uart_rx_impl(
            .clk(clk),
            .rst_n(rst),
            .rs232_rx(uart_tx_pin),
            .rx_done(uart_rx_done),
            .rx_data(uart_rx_data)
          );

  Computer computer(
             clk,
             rst,
             // uart
             uart_rx_pin,
             uart_tx_pin,
             // LED
             over,
             succ
           );

  initial
  begin
    clk = 1;
    forever
    begin
      #10;
      clk=~clk;
    end
  end

  initial
  begin
    rst = 1;
    rst = 0;
    repeat(10) @(posedge clk);
    rst = 1;

    repeat(1) @(posedge uart_rx_done);
    assert(uart_rx_data === 72) else
            $error("H failed");

    repeat(1) @(posedge uart_rx_done);
    assert(uart_rx_data === 101) else
            $error("e failed");

    repeat(1) @(posedge uart_rx_done);
    assert(uart_rx_data === 108) else
            $error("l failed");

    repeat(1) @(posedge uart_rx_done);
    assert(uart_rx_data === 108) else
            $error("l failed");

    repeat(1) @(posedge uart_rx_done);
    assert(uart_rx_data === 111) else
            $error("o failed");

    repeat(1) @(posedge uart_rx_done);
    assert(uart_rx_data === 44) else
            $error(", failed");

    repeat(1) @(posedge uart_rx_done);
    assert(uart_rx_data === 32) else
            $error("  failed");

    repeat(1) @(posedge uart_rx_done);
    assert(uart_rx_data === 119) else
            $error("w failed");

    repeat(1) @(posedge uart_rx_done);
    assert(uart_rx_data === 111) else
            $error("o failed");

    repeat(1) @(posedge uart_rx_done);
    assert(uart_rx_data === 114) else
            $error("r failed");

    repeat(1) @(posedge uart_rx_done);
    assert(uart_rx_data === 108) else
            $error("l failed");

    repeat(1) @(posedge uart_rx_done);
    assert(uart_rx_data === 100) else
            $error("d failed");

    repeat(1) @(posedge uart_rx_done);
    assert(uart_rx_data === 10) else
            $error("\\n failed");

    repeat(1) @(posedge uart_rx_done);
  end


endmodule
